	US 7,515,483 B2
	Page buffer flash memory device and programming method using the same
Jung Chul Han, Icheon-si (Korea, Republic of)
Assigned to Hynix Semiconductor Inc., Icheon-si (Korea, Republic of)
Filed on Jun. 30, 2006, as Appl. No. 11/480,330.
Claims priority of application No. 10-2005-0088097 (KR), filed on Sep. 22, 2005.
Prior Publication US 2007/0064485 A1, Mar. 22, 2007
Int. Cl. G11C 7/10 (2006.01)

U.S. Cl. 365—189.05 [365/185.21; 365/185.22; 365/185.11; 365/230.08]

20 Claims

3. A page buffer of a flash memory device including a memory cell array, the page buffer comprising:

a first bit line selection unit configured to select one of at least one pair of first bit lines coupled to the memory cell array and to connect the selected bit line to a first sensing line;

a second bit line selection unit configured to select one of at least one pair of second bit lines coupled to the memory cell array and to connect the selected bit line to a second sensing line;

a separation unit configured to disconnect the first sensing line and the second sensing line during a programming operation such that memory cells of the memory cell array corresponding to the selected first bit line and the selected second bit line are simultaneously programmed, and further configured to connect the first sensing line and the second sensing line during a cache program operation;

a precharge unit configured to precharge the first and second sensing lines;

a first register coupled to the first bit line selection unit through the first sensing line, the first register configured to latch a first input data;

a second register coupled to the second bit line selection unit through the second sensing line, the second register configured to latch a second input data; and

a third register coupled to the second bit line selection unit through the second sensing line, the third register configured to latch a third input data, wherein the first input data and the second input data are simultaneously programmed on memory cells corresponding to the selected first bit line and the selected second bit line, respectively, during the of latching the third input data on the third register such that the first input data and the second input data are programmed in the corresponding memory cells on a two-page basis.