an even bit line and an odd bit line for coupling to a memory cell array;

a register unit comprising a first register and a second register for temporarily storing data;

a detecting node for detecting a voltage level of a specific bit line or a specific register which is connected to the bit lines; and

a selecting unit comprising a first variable voltage input terminal and a second variable voltage terminal, wherein the first variable voltage input terminal applies a first variable voltage to the even bit line in response to an even discharge signal, and the second variable voltage input terminal applies a second variable voltage to the odd bit line in response to an odd discharge signal,

wherein the selecting unit pre-charges the even bit line and the odd bit line up to half of a first level voltage before coupling the detecting node to the bit line connected to a cell to be programmed,

wherein the first level voltage is applied to the bit line disconnected from the cell to be programmed when the detecting node is coupled to the bit line connected to the cell to be programmed.