| US 7,515,473 B2 | ||
| Semiconductor memory device | ||
| Koichi Fukuda, Yokohama (Japan); Midori Morooka, Yokohama (Japan); and Hiroyuki Dohmae, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Sep. 27, 2007, as Appl. No. 11/862,552. | ||
| Application 11/862552 is a continuation of application No. 11/412938, filed on Apr. 28, 2006, granted, now 7,277,325. | ||
| Claims priority of application No. 2005-130891 (JP), filed on Apr. 28, 2005; and application No. 2005-324847 (JP), filed on Nov. 09, 2005. | ||
| Prior Publication US 2008/0025101 A1, Jan. 31, 2008 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G11C 16/06 (2006.01) | ||
| U.S. Cl. 365—185.22 [365/185.09; 365/185.12] | 16 Claims |

| 1. A semiconductor memory device comprising:
a memory cell array with electrically rewritable and non-volatile memory cells arranged therein;
a sense amplifier circuit configured to read and write data of the memory cell array page by page;
a verify-judge circuit configured to judge write or erase completion based on verify-read data held in the sense amplifier
circuit; and
data latches disposed for the respective columns in the memory cell array to be connected to the verify-judge circuit, into
which column separation data are written to exclude the corresponding columns from a verifying object,
wherein during an initial set-up sequence at power-on, the column separation data in the data latches are first reset so that
the respective columns are included in the verifying object, and then the column separation data in the data latches are automatically
set so that in addition to defective columns at least a part of inaccessible columns for users are excluded from the verifying
object.
|