| US 7,515,469 B1 | ||
| Column redundancy RAM for dynamic bit replacement in FLASH memory | ||
| Alan Chen, Saratoga, Calif. (US); Neville Ichhaporia, San Jose, Calif. (US); Vijay P. Adusumilli, San Jose, Calif. (US); and Stephen Trinh, San Jose, Calif. (US) | ||
| Assigned to Atmel Corporation, San Jose, Calif. (US) | ||
| Filed on Sep. 27, 2007, as Appl. No. 11/862,436. | ||
| Int. Cl. G11C 16/06 (2006.01); G11C 16/04 (2006.01) | ||
| U.S. Cl. 365—185.09 [365/185.33] | 23 Claims |
| 1. A column redundancy system for a non-volatile memory, the system comprising:
a separate companion controller chip for controlling operational modes of the non-volatile memory chip, the separate companion
controller chip including a column redundancy RAM memory array for storing addresses of defective non-volatile memory cells;
column redundancy match logic configured to compare user input addresses for the non-volatile memory to addresses of defective
non-volatile memory cells stored in a column redundancy RAM memory array and configured to provide a match output signal corresponding
to a match of a particular user input address for the non-volatile memory with the address of a defective non-volatile memory
cell stored in the column redundancy RAM memory array; and
column redundancy replacement logic, in response to a match output signal from the column redundancy match logic, configured
to dynamically substitute correct data associated with a defective non-volatile memory cell into an I/O data bit stream of
a non-volatile memory chip.
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