| US 7,515,468 B2 | ||
| Nonvolatile memory device | ||
| Bo-Young Seo, Anyang-si (Korea, Republic of); Hee-Seog Jeon, Suwon-si (Korea, Republic of); Jeong-Uk Han, Suwon-si (Korea, Republic of); and Sung-Taeg Kang, Seoul (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., (Korea, Republic of) | ||
| Filed on Nov. 16, 2006, as Appl. No. 11/600,427. | ||
| Claims priority of application No. 10-2005-0110006 (KR), filed on Nov. 17, 2005. | ||
| Prior Publication US 2007/0195595 A1, Aug. 23, 2007 | ||
| Int. Cl. G11C 11/34 (2006.01) | ||
| U.S. Cl. 365—185.05 [365/63; 365/185.28] | 19 Claims |
| 1. A nonvolatile memory device having a plurality of memory cell units, the memory cell unit comprising:
a first impurity diffusion region and a second impurity diffusion region in an active region of a semiconductor substrate;
first and second memory gates on the active region between the first impurity diffusion region and the second impurity diffusion
region, the first and second memory gates each respectively adjacent to the first and second impurity diffusion regions;
one select gate on the active region between the first and second memory gates; and
first and second floating diffusion regions in the active region between the select gate and a corresponding one of the first
and second memory gates,
wherein the first memory gate, the second memory gate, and the select gate correspond to a first memory transistor, a second
memory transistor, and a select transistor, respectively.
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