US 7,515,186 B2
Pixel sensor
Alireza Moini, Balmain (Australia); Kia Silverbrook, Balmain (Australia); Paul Lapstun, Balmain (Australia); Peter Charles Boyd Henderson, Balmain (Australia); Zhenya Alexander Yourlo, Balmain (Australia); Matthew John Underwood, Balmain (Australia); and Nicholas Damon Ridley, Balmain (Australia)
Assigned to Silverbrook Research Pty Ltd, Balmain, New South Wales (Australia)
Filed on Feb. 17, 2004, as Appl. No. 10/778,059.
Claims priority of application No. 2003900746 (AU), filed on Feb. 17, 2003.
Prior Publication US 2005/0024512 A1, Feb. 03, 2005
Int. Cl. H04N 3/14 (2006.01); H04N 5/335 (2006.01); H01L 27/00 (2006.01)
U.S. Cl. 348—294  [348/302; 348/308; 250/208.1] 6 Claims
OG exemplary drawing
 
1. A photodetecting circuit comprising:
a photodetector for generating a signal in response to incident light;
a storage node having first and second node terminals;
a transfer transistor disposed intermediate the first node terminal and the photodetector, a control node of the transfer transistor receiving a transfer signal, such that when the transfer signal is asserted during an integration period of the photodetecting circuit, the first node terminal and the photodetector are electrically connected such that charge stored in the storage node changes the storage node during the integration period;
a reset transistor having a control node for receiving a reset signal, a first terminal for receiving a reset voltage, and a second terminal electrically connected to the first node terminal, such that the reset voltage is supplied to the first node terminal when the reset signal is asserted at the control node; and
an output circuit for generating an output signal during a read period of the photodetecting circuit, the output signal being at least partially based on a voltage at the first terminal;
the photodetecting circuit being configured to:
receive the reset signal;
integrate charge in the storage node during the integration period following receipt of the reset signal; and
receive a compensation signal at the second terminal of the storage node at least during the read period, the compensation signal increasing the voltage at the first terminal whilst the output circuit generates the output signal, wherein the compensation signal is a logically negated version of the transfer signal.