US 7,515,169 B2
Beam light scanning apparatus, image forming apparatus, and beam light scanning method
Kenichi Komiya, Kanagawa-Ken (Japan); Koji Tanimoto, Shizuoka-Ken (Japan); and Daisuke Ishikawa, Shizuoka-Ken (Japan)
Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan); and Toshiba Tec Kabushiki Kaisha, Tokyo (Japan)
Filed on Sep. 30, 2005, as Appl. No. 11/239,098.
Claims priority of application No. 2005-069856 (JP), filed on Mar. 11, 2005.
Prior Publication US 2006/0203077 A1, Sep. 14, 2006
Int. Cl. B41J 2/44 (2006.01)
U.S. Cl. 347—247 9 Claims
OG exemplary drawing
 
1. A beam light scanning apparatus comprising:
a light emitting unit configured to emit a beam light for scan;
an image data supplying unit configured to process and supply image data of a target image in each line in a direction of main scan in response to a sync signal;
a delayed acquisition unit configured to acquire the image data supplied from the image data supplying unit after a certain time from generation of the sync signal; and
a control unit configured to control operation of the light emitting means by a driving signal which is generated based on the image data outputted from the delayed acquisition unit,
wherein the delayed acquisition unit comprises:
two first-in, first-out memory memories for separately storing the image data of odd-numbered pixels and even-numbered pixels in each line,
a writing unit configured to write the image data supplied from the image data supplying unit into the two memories in a manner separated into the odd-numbered pixels and the even-numbered pixels, and
a reading unit configured to read the image data written in the two memories after the certain time in a manner separated into the odd-numbered pixels and the even-numbered pixels, and
a combining unit configured to combine the image data of the odd-numbered pixels and the even-numbered pixels read by the reading unit into image data having the same order as an original data train,
wherein a frequency of a write data clock of the two memories is a half of a frequency of a data read clock of the two memories, and
wherein a writing pointer and a reading pointer of the two memories are cleared whenever one line has been formed in synchronism with the sync signal.