| US 7,515,079 B2 | ||
| Method of controlling delta-sigma modulator and delta-sigma modulator | ||
| Tomoaki Maeda, Kyoto (Japan); Hisashi Adachi, Osaka (Japan); and Taiji Akizuki, Miyagi (Japan) | ||
| Assigned to Panasonic Corporation, Osaka (Japan) | ||
| Filed on Sep. 06, 2007, as Appl. No. 11/896,816. | ||
| Claims priority of application No. P. 2006-244378 (JP), filed on Sep. 08, 2006. | ||
| Prior Publication US 2008/0062024 A1, Mar. 13, 2008 | ||
| Int. Cl. H03M 3/00 (2006.01) | ||
| U.S. Cl. 341—143 [341/144] | 4 Claims |
| 1. A delta-sigma modulator including integrators cascade-connected at a plurality of stages, a quantizer for quantizing an
output signal of the integrator at a last stage, a DA converter for returning an output signal of the quantizer to inputs
of the integrators at a plurality of stages, and a local feedback unit that contains two integrators or more out of the integrators
at the plurality of stages and needs no interposition of the quantizer, comprising:
a first delay unit for delaying output signals of the DA converter by a half period of a clock; and
a second delay unit for delaying an output signal of the local feedback unit by the half period of the clock;
wherein the delta-sigma modulator operates at timings of a double sampling;
the integrators at a plurality of stages are constructed by cascade-connecting first to third integrators,
the first integrator includes a third delay unit for delaying the input signal by the half period of the clock, and a first
adder for subtracting the output signals of the DA converter from an output signal of the third delay unit,
the second integrator includes a fourth delay unit for delaying an output signal of the first integrator by the half period
of the clock, and a second adder for subtracting the output signals of the DA converter and an output signal of the local
feedback unit from an output signal of the fourth delay unit, and
the third integrator includes a third adder for subtracting the output signals of the DA converter from an output signal of
the second integrator.
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