a VCO unit generating, at an oscillation frequency and according to a control voltage, first and second signals having a 180° phase difference from each other to output the first and second signals through first and second oscillation output terminals, respectively; and

a duty correction unit generating a clock signal of a 50% duty according to the first and second signals outputted through the first and second oscillation terminals;

wherein

the VCO unit comprises more than three delay cells of a ring-type oscillation structure, each of the delay cells having first and second input terminals receiving two input signals with a phase difference of a half period from each other, and first and second output terminals, the delay cell delaying the two input signals received through the first and second input terminals for a predetermined delay time according to the control voltage, and then outputting the signals though the first and second output terminals;

a total number of the delay cells in the VCO unit is an odd number and the delay cells are connected in series;

the first input terminal of any delay cell other than a beginning delay cell in the series is connected to the second output terminal of a previous delay cell in the series, wherein the first input terminal and the second output terminal are reversed in phase relative to each other;

the second input terminal of said any delay cell is connected to the first output terminal of the previous delay cell, wherein the second input terminal and the first output terminal are reversed in phase relative to each other; and

the first and second output terminals of an end delay cell in the series are connected in a positive feedback to the first and second input terminals, respectively, of the beginning delay cell.