| US 7,514,974 B2 | ||
| Method and apparatus for adjusting on-chip delay with power supply control | ||
| Stefan G. Block, Munich (Germany); and Stephan Habel, Berg (Germany) | ||
| Assigned to LSI Corporation, Milpitas, Calif. (US) | ||
| Filed on Apr. 18, 2007, as Appl. No. 11/736,931. | ||
| Prior Publication US 2008/0258700 A1, Oct. 23, 2008 | ||
| Int. Cl. H03L 7/00 (2006.01) | ||
| U.S. Cl. 327—161 [327/162] | 18 Claims |
| 1. An apparatus comprising:
an integrated circuit chip comprising a ring oscillator having a clock output;
a clock source, which provides a reference clock;
a voltage regulator, which is external to the integrated circuit chip and provides the chip with a supply voltage having a
level based on a control signal; and
a comparator circuit, which supplies the control signal to the voltage regulator based on a comparison between a frequency
of the clock output and a frequency of the reference clock, the comparator circuit comprising:
a first counter, which generates a first count as a function of the clock output frequency;
a second counter, which generates a second count as a function of the reference clock frequency; and
a control circuit, which generates the control signal based on the first and second counts, and wherein at least one of the
first or second counters is coupled to stop the other of the first or second counters from counting upon the respective first
or second count reaching a predetermined count.
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