| US 7,514,763 B2 | ||
| Semiconductor device and manufacturing method for the same | ||
| Masafumi Hamaguchi, Kawasaki (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Minato-Ku, Tokyo (Japan) | ||
| Filed on Oct. 30, 2007, as Appl. No. 11/928,750. | ||
| Application 11/826117 is a division of application No. 11/079520, filed on Mar. 15, 2005, granted, now 7,271,443. | ||
| Application 11/928750 is a continuation of application No. 11/826117, filed on Jul. 12, 2007. | ||
| Claims priority of application No. 2004-245293 (JP), filed on Aug. 25, 2004. | ||
| Prior Publication US 2008/0067633 A1, Mar. 20, 2008 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. H01L 29/167 (2006.01); H01L 29/207 (2006.01); H01L 29/227 (2006.01); H01L 31/0288 (2006.01) | ||
| U.S. Cl. 257—607 [257/344; 257/345; 438/199; 438/286] | 11 Claims |
| 1. A semiconductor device, comprising:
a semiconductor substrate;
a gate insulating film provided on the semiconductor substrate;
a gate electrode provided on the gate insulating film;
a sidewall spacer provided on side walls of the gate insulating film and the gate electrode;
an extension region including germanium atoms and first impurity atoms, provided on a surface layer of the semiconductor substrate
on both sides of the gate insulating film, the first impurity atoms are coexisting with the germanium atoms in an entirety
of the extension region, the first impurity atoms contributing to electric conductivity; and
a diffusion region including second impurity atoms, provided on an upper side of the extension region at a depth more shallow
than the extension region from a surface of the extension region, the second impurity atoms not contributing to the electric
conductivity.
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