| US 7,514,742 B2 | ||
| Recessed shallow trench isolation | ||
| Chih Chieh Yeh, Taipei (Taiwan); and Wen Jer Tsai, Hualien (Taiwan) | ||
| Assigned to Macronix International Co., Ltd., Hsinchu (Taiwan) | ||
| Filed on Oct. 13, 2005, as Appl. No. 11/249,228. | ||
| Prior Publication US 2007/0087523 A1, Apr. 19, 2007 | ||
| Int. Cl. H01L 27/108 (2006.01) | ||
| U.S. Cl. 257—326 [257/314; 438/435] | 17 Claims |
| 1. A memory integrated circuit, comprising:
memory circuitry including memory circuitry trenches, including:
first shallow trench isolation structures including first isolation dielectric, the first isolation dielectric filling the
memory circuitry trenches incompletely, the memory circuitry trenches characterized a first trench depth between top edge
to bottom; and
control circuitry coupled to the memory circuitry, the control circuitry including control circuitry trenches, including:
second shallow trench isolation structures including second isolation dielectric, the second isolation dielectric filling
the control circuitry trenches more completely than the first isolation dielectric fills the memory circuitry trenches, the
control circuitry trenches characterized a second trench depth between top edge to bottom, the second trench depth having
a magnitude larger than the first trench depth.
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