| US 7,514,728 B2 | ||
| Semiconductor integrated circuit device using four-terminal transistors | ||
| Takeshi Sugahara, Fujisawa (Japan); and Yasuhito Itaka, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Nov. 30, 2007, as Appl. No. 11/948,350. | ||
| Application 11/948350 is a division of application No. 11/166243, filed on Jun. 27, 2005, granted, now 7,365,377. | ||
| Claims priority of application No. 2005-058736 (JP), filed on Mar. 03, 2005. | ||
| Prior Publication US 2008/0073729 A1, Mar. 27, 2008 | ||
| Int. Cl. H01L 27/10 (2006.01); H01L 29/73 (2006.01) | ||
| U.S. Cl. 257—206 [257/202; 257/203; 257/204; 257/210; 257/371; 257/E27.06; 257/E27.108; 257/E27.11] | 2 Claims |
| 1. A semiconductor integrated circuit device comprising:
a semiconductor substrate of a first conductivity type;
a first well region of the first conductivity type which is formed in a first region of the semiconductor substrate;
a plurality of second well regions of a second conductivity type which are formed in the first region of the semiconductor
substrate excluding the region where the first well region has been formed;
a third well region of the second conductivity type which is formed under the first and second well regions in the first region
of the semiconductor substrate in such a manner that a part of the third well region under the first well region is removed
and which connects the second well regions to one another electrically, the third well region is shaped like a lattice;
a fourth well region of the first conductivity type which is formed in a second region of the semiconductor substrate;
a fifth well region of the second conductivity type which is formed in the second region of the semiconductor substrate so
as to enclose the fourth well region;
a sixth well region which is formed under the fourth and fifth well regions in the semiconductor substrate so as to separate
the fourth well region from the semiconductor substrate electrically;
a first group of MOS transistors which is formed in each of the first and second well regions and operates on a first power
supply voltage;
a second group of MOS transistors which is formed in each of the fourth and fifth well regions and operates on a second power
supply voltage;
at least one first terminal which applies a first bias potential to the first well region;
at least one second terminal which applies a second bias potential to the second and third well regions; and
at least one third terminal which applies a third bias potential to the fourth well region.
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