| US 7,514,356 B2 | ||
| Ribs for line collapse prevention in damascene structures | ||
| Sajan Marokkey, Wappingers Falls, N.Y. (US); O Seo Park, Hopewell Junction, N.Y. (US); Wai-Kin Li, Poughkeepsie, N.Y. (US); and Todd C. Bailey, Fishkill, N.Y. (US) | ||
| Assigned to Infineon Technologies AG, Munich (Germany); and International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Mar. 01, 2005, as Appl. No. 11/69,068. | ||
| Prior Publication US 2006/0199369 A1, Sep. 07, 2006 | ||
| Int. Cl. H01L 21/4763 (2006.01) | ||
| U.S. Cl. 438—638 [257/E21.579] | 22 Claims |
| 1. A method of fabricating a semiconductor device, the method comprising:
depositing a first insulating layer over a workpiece;
patterning the first insulating layer forming recess for vias in the first insulating layer;
depositing a second insulating layer on the first insulating layer;
depositing a masking material of a first thickness over the second insulating layer;
patterning the masking material with a pattern for a damascene structure, the pattern comprising a resist line and ribs extending
from the resist line, wherein the resist line is oriented along a first direction, and parallel to a first and a second dummy
via, wherein the ribs are disposed along a line parallel to the first direction, wherein a single rib of the ribs is disposed
between the first and the second dummy vias, wherein the resist line comprises a first top critical dimension between the
first dummy via and a third dummy via along a second direction, the second direction being perpendicular to the first direction,
wherein the resist line comprises a second top critical dimension between the ribs along the second direction, the second
top critical dimension being wider than the first top critical dimension;
etching recesses for metal lines using the resist line as a mask; and
filling the recesses for metal lines and vias with conductive material.
|