a gate line and a gate electrode formed on a substrate, the gate line and the gate electrode being formed of a stack of a first gate line layer and a second gate line layer;

a gate insulating layer on the gate electrode;

a data line crossing the gate line on the gate insulating layer to define a pixel region;

source and drain electrodes partially overlapping the gate electrode;

an organic semiconductor layer on the source and drain electrodes and the data line;

a passivation layer on the organic semiconductor layer including a contact hole exposing the drain electrode; and

a pixel electrode on the passivation layer and connected through the contact hole to the drain electrode, wherein the first gate line layer includes a cut portion,

wherein the source electrode protrudes from the data line.