| US 7,514,310 B2 | ||
| Dual work function metal gate structure and related method of manufacture | ||
| Min-Joo Kim, Gyeonggi-do (Korea, Republic of); Hyung-Suk Jung, Gyeonggi-do (Korea, Republic of); Jong-Ho Lee, Gyeonggi-do (Korea, Republic of); and Sungkee Han, Seongnam-si (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do (Korea, Republic of) | ||
| Filed on Jul. 29, 2005, as Appl. No. 11/192,288. | ||
| Claims priority of provisional application 60/631887, filed on Dec. 01, 2004. | ||
| Claims priority of application No. 10-2005-0014719 (KR), filed on Feb. 22, 2005. | ||
| Prior Publication US 2006/0115940 A1, Jun. 01, 2006 | ||
| Int. Cl. H01L 21/8238 (2006.01) | ||
| U.S. Cl. 438—199 [257/407; 257/E21.632] | 40 Claims |
| 15. A method, comprising:
forming an NMOS active region and a PMOS active region in a substrate;
forming a gate insulating layer on the substrate covering the NMOS active region and the PMOS active region;
forming a metal layer having a first work function on the gate insulating layer;
adjusting the first work function in a selected portion of the metal layer by doping the selected portion with either fluorine
to decrease the first work function or carbon to increase the first work function, such that the selected portion has a second
work function different from the first work function.
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