| US 7,353,448 B1 | ||
| Methods, architectures, circuits and systems for transmission error determination | ||
| Dror Barash, Rannana (Israel) | ||
| Assigned to Marvell Semiconductor Israel Ltd., Misgav (Israel) | ||
| Filed on Oct. 21, 2003, as Appl. No. 10/690,780. | ||
| Int. Cl. H03M 13/00 (2006.01); G01R 31/28 (2006.01) | ||
| U.S. Cl. 714—781 [714/758; 714/776; 714/712] | 63 Claims |
| 1. A method of checking digital information for a transmission error, comprising the steps of:
a) receiving said digital information, said digital information comprising a plurality of data portions and a further portion
containing data and non-data, each of the data portions and the further portion having a fixed first length;
b) removing said non-data from the further portion to generate a remainder having a second length less than said fixed first
length;
c) adding a zero-pad vector to said remainder to generate a zero-padded data portion having said fixed first length; and
d) checking said plurality of data portions and said zero-padded data portion for a transmission error.
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