| US 7,353,444 B2 | ||
| LDPC architecture | ||
| Patrick A. Owsley, Moscow, Id. (US); Brian A. Banister, Pullman, Wash. (US); and Tom Hansen, Pullman, Wash. (US) | ||
| Assigned to Comtech AHA Corporation, Moscow, Id. (US) | ||
| Filed on May 06, 2005, as Appl. No. 11/123,671. | ||
| Claims priority of provisional application 60/568939, filed on May 07, 2004. | ||
| Prior Publication US 2005/0258984 A1, Nov. 24, 2005 | ||
| Int. Cl. H03M 13/45 (2006.01) | ||
| U.S. Cl. 714—752 [714/780] | 35 Claims |
| 1. An iterative decoder structure allowing parallel evaluation of parity equations comprising:
a. received data inputs,
b. a permuter to receive the received data inputs and current array outputs, and to generate a permuter output,
c. a first adder, wherein the first adder receives the permuter output as a first input to the first adder and a difference
array output as a second input to the first adder and generates a first adder output,
d. a processor, wherein the processor receives the first adder output and generates an estimate output and a difference output,
e. a difference array, wherein the difference array receives the difference output and outputs a difference array output,
and
f. a current array, wherein the current array receives the estimate output and presents a current array output to the permuter.
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