| US 7,353,329 B2 | ||
| Memory buffer device integrating refresh logic | ||
| Robert M. Ellis, Hillsboro, Oreg. (US); Kuljit S. Bains, Olympia, Wash. (US); Chris B. Freeman, Portland, Oreg. (US); John B. Halbert, Beaverton, Oreg. (US); Narendra S. Khandekar, Folsom, Calif. (US); and Michael W. Williams, Citrus Heights, Calif. (US) | ||
| Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
| Filed on Sep. 29, 2003, as Appl. No. 10/674,981. | ||
| Prior Publication US 2005/0071543 A1, Mar. 31, 2005 | ||
| Int. Cl. G06F 12/16 (2006.01) | ||
| U.S. Cl. 711—106 [365/222; 365/228] | 31 Claims |
| 1. A memory device comprising:
a storage array comprised of a plurality of memory cells organized into an array of rows;
an interface buffer coupled to the storage array, and having a first interface to couple the memory device to a first memory
bus to couple the memory device to an external memory controller; and
refresh logic associated with the interface buffer to carry and a refresh operation on a row within the storage array during
a period of time in which there are no transactions carried out by the external memory controller on the first memory bus
that involve the storage array, the refresh logic to detect a pattern of activity on the first memory bus to identify a time
to carry out the refresh operations and to determine which device of a plurality of devices will control the refresh operation.
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