US 7,353,301 B2
Methodology and apparatus for implementing write combining
Sivakumar Radhakrishnan, Portland, Oreg. (US); Siva Balasubramanian, Chandler, Ariz. (US); William T. Futral, Portland, Oreg. (US); Sujoy Sen, Portland, Oreg. (US); Gregory D. Cummings, Portland, Oreg. (US); Kenneth C. Creta, Gig Harbor, Wash. (US); and David C. Lee, Beaverton, Oreg. (US)
Assigned to Intel Corporation, Santa Clara, Calif. (US)
Filed on Oct. 29, 2004, as Appl. No. 10/977,235.
Prior Publication US 2006/0095609 A1, May 04, 2006
Int. Cl. G06F 3/00 (2006.01); G06G 3/00 (2006.01)
U.S. Cl. 710—33  [710/30] 26 Claims
OG exemplary drawing
 
1. A method comprising:
detecting a write transaction request directed to a input/output (I/O) device;
storing data associated with the detected write transaction within a buffer assigned to a write-combinable range if a transaction address associated with the detected write transaction falls within the write-combinable range for the I/O device;
creating one or more packets having a descriptor and the data associated with detected write transactions stored in the buffer in response to a flush request to flush the buffer;
sending the one or more packets to the I/O device;
setting a new buffer after flushing contents of the buffer; and
tracking byte enables of all transactions that fall within the write combining range associated with the buffer, wherein each bit of a byte enable vector corresponds to a distinct portion of the buffer, and further wherein each bit being set indicates the distinct portion of the buffer that includes data associated with a write transaction.