| US 7,352,229 B1 | ||
| Reference clock receiver compliant with LVPECL, LVDS and PCI-Express supporting both AC coupling and DC coupling | ||
| Haitao Mei, Kanata (Canada); Shoujun Wang, Kanata (Canada); William Bereza, Nepean (Canada); and Mirza Baig, Nepean (Canada) | ||
| Assigned to Altera Corporation, San Jose, Calif. (US) | ||
| Filed on Jul. 10, 2006, as Appl. No. 11/484,366. | ||
| Int. Cl. H03L 5/00 (2006.01) | ||
| U.S. Cl. 327—333 [327/306] | 21 Claims |
| 1. A reference clock receiver structure comprising:
an input buffer comprising a PMOS differential pair of transistors and a first supply voltage, the PMOS differential pair
of transistors receiving a pair of differential inputs and producing a pair of differential outputs;
a level shifter that is coupled to receive the pair of differential outputs from the input buffer to provide gain to the pair
of differential outputs to form a gained pair of differential outputs, the level shifter that comprises a second supply voltage,
the second supply voltage having a smaller magnitude than the first supply voltage; and
a CMOS buffer that is coupled to receive the gained pair of differential outputs, to boost the gained pair of differential
outputs and to convert the gained differential pair outputs into a single signal.
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