| US 7,352,228 B2 | ||
| Method and apparatus of a level shifter circuit with duty-cycle correction | ||
| Shahid Ali, Bangalore (India); Sujan Manohar, Karnataka (India); and Satheesh Balasubramanian, Bangalore (India) | ||
| Assigned to Texas Instruments Incorporated, Dallas, Tex. (US) | ||
| Filed on May 03, 2006, as Appl. No. 11/416,608. | ||
| Prior Publication US 2007/0257722 A1, Nov. 08, 2007 | ||
| Int. Cl. H03L 5/00 (2006.01) | ||
| U.S. Cl. 327—333 [327/315; 326/60; 326/61; 326/62; 326/63; 326/80; 326/83] | 18 Claims |
| 1. A system, comprising:
a first circuit to operate based on a first voltage of a first power supply;
a second circuit to operate based on a second voltage of a second power supply;
a level shifter circuit between the first circuit and the second circuit to translate between the first voltage of the first
power supply and the second voltage of the second power supply; and
the level shifter circuit comprises a n-channel metal-oxide semiconductor field-effect transistor (nMOSFET) having a gate
input of the second voltage and serially coupled in a fall path of the level shifter circuit to increase a rate of a capacitive
discharge such that the rate of a capacitive discharge charge is substantially equal to a rate of a capacitive charge.
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