| US 7,352,004 B2 | ||
| Thin film transistor array panel and method for manufacturing the same | ||
| Je-Hun Lee, Seoul (Korea, Republic of); Yang-Ho Bae, Suwon-si (Korea, Republic of); Beom-Seok Cho, Seoul (Korea, Republic of); and Chang-Oh Jeong, Suwon-si (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., (Korea, Republic of) | ||
| Filed on Oct. 14, 2005, as Appl. No. 11/249,500. | ||
| Claims priority of application No. 10-2004-0085683 (KR), filed on Oct. 26, 2004. | ||
| Prior Publication US 2006/0091396 A1, May 04, 2006 | ||
| Int. Cl. H01L 29/04 (2006.01); H01L 29/10 (2006.01); H01L 31/00 (2006.01) | ||
| U.S. Cl. 257—59 [257/72; 257/350; 257/E51.005; 257/E51.022] | 12 Claims |
| 1. A thin film transistor (TFT) array panel, comprising:
an insulating substrate;
a gate line formed on the insulating substrate, the gate line having a first layer that includes Al, a second layer that includes
Cu containing metal and is thicker than the first layer, and a gate electrode;
a gate insulating layer arranged on the gate line;
a semiconductor arranged on the gate insulating layer;
a data line having a source electrode, the data line being arranged on the gate insulating layer and the semiconductor;
a drain electrode arranged on the gate insulating layer and the semiconductor and facing the source electrode;
a passivation layer having a contact hole, the passivation layer arranged on the data line and the drain electrode; and
a pixel electrode arranged on the passivation layer and coupled with the drain electrode.
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