| US 7,512,924 B2 | ||
| Semiconductor device structure and methods of manufacturing the same | ||
| Hsien-Wei Chen, Sinying (Taiwan); Hsueh-Chung Chen, Yonghe (Taiwan); Yi-Lung Cheng, Danshuei Township, Taipei County (Taiwan); and Shin-Puu Jeng, Hsinchu (Taiwan) | ||
| Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (Taiwan) | ||
| Filed on Jan. 17, 2006, as Appl. No. 11/333,618. | ||
| Prior Publication US 2007/0166887 A1, Jul. 19, 2007 | ||
| Int. Cl. G06F 17/50 (2006.01) | ||
| U.S. Cl. 716—18 | 16 Claims |
| 1. A method performed by a machine for generating a layout for a semiconductor device array, comprising:
providing a first layout comprising a plurality of active conductive features, each one of the plurality of active conductive
features being surrounded by a respective boundary area, and an open area consisting of areas of the first layout that not
occupied by any one of the plurality of active conductive features and its respective boundary area;
providing a plurality of dummy templates of different pattern densities, each of which comprises a plurality of dummy seeds;
generating a second layout by integrating one of the dummy templates into the first layout and deleting any one of the plurality
of dummy seeds within the integrated dummy template overlapping any one of the plurality of active conductive features or
its respective boundary area, whereby a plurality of dummy seeds remain in the open area of the second layout; and physcially
applying the second layout to a semiconductor device array.
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