US 7,512,916 B2
Electrostatic discharge testing method and semiconductor device fabrication method
Sachio Hayashi, Tokyo (Japan)
Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan)
Filed on Oct. 03, 2005, as Appl. No. 11/243,355.
Claims priority of application No. P2004-294961 (JP), filed on Oct. 07, 2004.
Prior Publication US 2006/0109596 A1, May 25, 2006
Int. Cl. G06F 17/50 (2006.01); H02H 9/00 (2006.01)
U.S. Cl. 716—5  [716/4; 716/12; 361/56] 20 Claims
OG exemplary drawing
 
1. A method for determining a layout which passes testing for electrostatic discharge in a semiconductor device, comprising:
extracting an electrostatic discharge protection network comprising pads, nets and protective elements from the layout of the semiconductor device;
setting start pads and end pads from the pads in the electrostatic discharge protection network;
detecting inter-pad voltages between the start pads and the end pads and electrostatic discharge current paths along which the nets and the protective elements are arranged in a sequential order from the start pads to the end pads;
grouping, via a grouping process, the electrostatic discharge current paths along with the nets and the protective elements arranged in the sequential order of the detecting the inter-pad voltages step, wherein the grouping process includes grouping the electrostatic discharge current paths as a function of corresponding sequential order of names of elements in the one electrostatic discharge current oath including one or more of names for I/O cells connected to pads, net names, protective element names, or names for I/O cells to which protective elements belong;
calculating estimated values of electrostatic discharge withstand voltages between the start pads and the end pads, based on the inter-pad voltages between the start pads and the end pads and groups to which the start pads and the end pads belong, using a negative correlation between the inter-pad voltages and corresponding electrostatic withstand voltages for each group; and
providing a result indicating determination of whether the layout passes testing for electrostatic discharge, based on the estimated values.