| US 7,512,867 B2 | ||
| Method for encoding/decoding error correcting code, transmitting apparatus and network | ||
| Masaki Ohira, Yokohama (Japan); Masahiro Takatori, Yokohama (Japan); and Takashi Mori, Yokohama (Japan) | ||
| Assigned to Hitachi, Ltd, Tokyo (Japan) | ||
| Filed on Jan. 30, 2006, as Appl. No. 11/344,579. | ||
| Application 11/344579 is a division of application No. 09/771733, filed on Jan. 29, 2001, granted, now 7,024,616. | ||
| Claims priority of application No. 2000-179377 (JP), filed on Jun. 09, 2000. | ||
| Prior Publication US 2006/0212780 A1, Sep. 21, 2006 | ||
| Int. Cl. H03M 13/03 (2006.01) | ||
| U.S. Cl. 714—786 [714/772; 714/773] | 23 Claims |
| 1. A method for decoding a super FEC (forward error correction) signal while correcting errors in said super FEC signal, said
super FEC signal having a predetermined frame structure, a predetermined overhead area, and a predetermined error correcting
code, said method comprising the steps of:
repeatedly parallelizing said super FEC signal to G systems every L consecutive bits to generate G parallelized FEC signals;
detecting a framing pattern inserted in said overhead area to adjust a temporal sequence and a parallel sequence of said parallelized
FEC signal to reconstruct a sequence of a scrambled inner encoded block; and
performing predetermined descrambling on said scrambled inner encoded block to reconstruct an inner encoded block, wherein
L is a predetermined integer value and G is an integer indicating the number of systems.
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