| US 7,512,850 B2 | ||
| Checkpointing user design states in a configurable IC | ||
| Jason Redgrave, Mountain View, Calif. (US); Brad Hutchings, Fremont, Calif. (US); Herman Schmit, Palo Alto, Calif. (US); Steven Teig, Menlo Park, Calif. (US); and Tom Kronmiller, Chapel Hill, N.C. (US) | ||
| Assigned to Tabula, Inc., Santa Clara, Calif. (US) | ||
| Filed on Mar. 13, 2006, as Appl. No. 11/375,370. | ||
| Claims priority of provisional application 60/699463, filed on Jul. 15, 2005. | ||
| Prior Publication US 2008/0222465 A1, Sep. 11, 2008 | ||
| Int. Cl. G01R 31/28 (2006.01) | ||
| U.S. Cl. 714—725 [714/724; 714/25; 714/742; 716/16; 716/17; 326/16; 326/17] | 18 Claims |
| 1. The method of debugging a configurable integrated circuit (IC), the method comprising:
a) iteratively starting and stopping a user-design operation of the IC;
b) at each particular stoppage, retrieving a plurality of user-design state values associated with a user-design state of
the IC at the particular stoppage without retrieving configuration data;
c) storing the retrieved user-design state values;
d) encountering an error in the operation of the IC;
e) reloading in the IC the stored user-design state values associated with a stoppage prior to encountering the error; and
f) after reloading the user-design state values, re-starting the operation of the IC and monitoring the operation of the IC
to identify a source for the error.
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