| US 7,512,759 B2 | ||
| Memory device | ||
| Yoshiaki Nakanishi, Suginami-ku (Japan); and Yoshihiko Takagi, Oota-ku (Japan) | ||
| Assigned to Panasonic Corporation, Osaka (Japan) | ||
| Appl. No. 10/549,028 PCT Filed Mar. 23, 2004, PCT No. PCT/JP2004/003943 § 371(c)(1), (2), (4) Date Sep. 15, 2005, PCT Pub. No. WO2004/086234, PCT Pub. Date Oct. 07, 2004. |
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| Claims priority of application No. 2003-085298 (JP), filed on Mar. 26, 2003. | ||
| Prior Publication US 2006/0200864 A1, Sep. 07, 2006 | ||
| Int. Cl. G06F 12/12 (2006.01) | ||
| U.S. Cl. 711—163 [717/158] | 10 Claims |
| 1. A memory device comprising:
a secure area inaccessible directly from an electronic device;
a secure control section which manages access to the secure area; and
a device control section which communicates with the electronic device and transfers a request from the electronic device
to the secure control section,
wherein the secure control section temporarily delegate, to the device control section, access rights to the secure area if
there is a write or read request of large capacity data from an authenticated electronic device, and
wherein the device control section to which the access rights have been delegated writes data sent from the electronic device
into the secure area by burst transfer, or sends data read from the secure area to the electronic device by burst transfer.
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