US 7,512,647 B2
Condensed Galois field computing system
James Wilson, Foxboro, Mass. (US); Yosef Stein, Sharon, Mass. (US); and Joshua Kablotsky, Sharon, Mass. (US)
Assigned to Analog Devices, Inc., Norwood, Mass. (US)
Filed on Nov. 22, 2004, as Appl. No. 10/994,699.
Prior Publication US 2006/0123325 A1, Jun. 08, 2006
Int. Cl. G06F 15/00 (2006.01)
U.S. Cl. 708—492 13 Claims
OG exemplary drawing
 
1. A condensed Galois field computing system comprising:
a multiplier circuit for multiplying first and second polynomials with coefficients over a Galois field to obtain their product; and
a Galois field transformer circuit for applying an irreducible polynomial of power n to said product including a partial result generator responsive to terms of power n and greater in said product for providing a folded partial result and a Galois field adder for combining said folded partial result and the terms less than power n in the product to obtain Galois field transform of power n of said product, said partial result generator including a look-up table that includes the folded partial results for the terms with the power of n or greater, the computing system used for error correction and/or encryption.