| US 7,512,501 B2 | ||
| Defect inspecting apparatus for semiconductor wafer | ||
| Hiroyuki Morinaga, Yokohama (Japan); Atsushi Onishi, Yokkaichi (Japan); Masayoshi Yamasaki, Oita (Japan); Takema Ito, Yokohama (Japan); and Yasuhiro Kaga, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Aug. 16, 2007, as Appl. No. 11/889,765. | ||
| Claims priority of application No. 2006-225284 (JP), filed on Aug. 22, 2006. | ||
| Prior Publication US 2008/0052021 A1, Feb. 28, 2008 | ||
| Int. Cl. G01B 5/28 (2006.01); G01B 5/30 (2006.01) | ||
| U.S. Cl. 702—35 [702/81; 702/117; 702/189; 257/E21.53; 438/6; 438/48] | 20 Claims |
| 1. A defect inspecting apparatus comprising:
an inspection region dividing section which divides a defect inspection region of a wafer on which a circuit pattern is formed
into a plurality of inspection subregions;
a pattern density calculating section which calculates the pattern density of each of the inspection subregions on the basis
of design data of the circuit pattern;
an inspection execution region and sensitivity rank setting section which assigns a sensitivity rank to each of the plurality
of inspection subregions on the basis of the pattern density, and groups the plurality of inspection subregions which are
adjacent to each other and which have the same sensitivity rank to set an inspection execution region; and
a defect inspecting section which sets an inspection parameter on the basis of sensitivity ranks of the inspection execution
regions and inspects the inspection execution regions for a defect.
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