US 7,512,386 B2
	Method and apparatus providing integrated load matching using adaptive power amplifier compensation
Sami Kalajo, Helsinki (Finland); Esko Jarvinen, Espoo (Finland); Ville Vintola, Espoo (Finland); Frank Anthony Tamborino, Summerfield, N.C. (US); and William Sheridan Kopp, Greensboro, N.C. (US)
Assigned to Nokia Corporation, Espoo (Finland); and RF Micro Devices, Inc., Greensboro, N.C. (US)
Filed on Aug. 29, 2003, as Appl. No. 10/651,910.
Prior Publication US 2005/0059362 A1, Mar. 17, 2005
Int. Cl. H04B 1/04 (2006.01); H04B 17/00 (2006.01); H03C 1/62 (2006.01); H01Q 11/12 (2006.01)

U.S. Cl. 455—127.1  [455/117]

25 Claims

1. A power amplifier module operable over a range of output power levels, comprising an output transistor having an input coupled to an input node of the power amplifier module and an output coupled to an output node of the power amplifier module, the power amplifier module further comprising circuitry for automatically compensating a load line of the output transistor for impedance variations appearing at the output node, the circuitry comprising detection circuitry for generating a first detection signal having a value that is indicative of the current flowing through the output transistor and a second detection signal having a value that is indicative of the voltage appearing at the output of the output transistor, and further comprising compensation circuitry for controlling the generation of a plurality of power amplifier bias current and bias voltage signals to have values that are a function of the values of the first and second detection signals, and the current output power level of the power amplifier module.