US 7,512,173 B2
Low I/O bandwidth method and system for implementing detection and identification of scrambling codes
Sharad Sambhwani, San Diego, Calif. (US); and Ghobad Heidari, San Diego, Calif. (US)
Assigned to QST Holdings, LLC, Palo Alto, Calif. (US)
Filed on Mar. 13, 2007, as Appl. No. 11/724,076.
Application 11/724076 is a continuation of application No. 10/295692, filed on Nov. 14, 2002, granted, now 7,215,701.
Application 10/295692 is a continuation in part of application No. 10/015531, filed on Dec. 12, 2001, granted, now 7,088,825.
Prior Publication US 2007/0153883 A1, Jul. 05, 2007
This patent is subject to a terminal disclaimer.
Int. Cl. H04B 1/00 (2006.01)
U.S. Cl. 375—150 49 Claims
OG exemplary drawing
 
1. A system for identifying a scrambling code in received signals comprising:
a scrambling code generator configured to generate a plurality of X-component segments forming a plurality of X-component sequential chips of a master scrambling code and configured to generate a plurality of Y-component segments forming a plurality of Y-component sequential chips of the master scrambling code; and
a plurality of correlators configured to correlate in parallel the received signals with corresponding X-component and Y-component segments, a first correlator of the plurality of correlators configured to receive a next corresponding X-component segment generated by the scrambling code generator, each remaining correlator of the plurality of correlators configured to receive its next corresponding X-component segment from another correlator of the plurality of correlators, and each correlator of the plurality of correlators is configured to receive a next corresponding Y-component segment generated by the scrambling code generator.