| US 7,512,013 B2 | ||
| Memory structures for expanding a second bit operation window | ||
| Chao-I Wu, Zhubei (Taiwan) | ||
| Assigned to Macronix International Co., Ltd, Hsinchu (Taiwan) | ||
| Filed on Jun. 21, 2006, as Appl. No. 11/425,523. | ||
| Prior Publication US 2007/0297243 A1, Dec. 27, 2007 | ||
| Int. Cl. G11C 11/03 (2006.01) | ||
| U.S. Cl. 365—185.28 [365/185.13; 365/185.24; 365/185.26; 365/185.29] | 14 Claims |
| 1. A memory device for increasing a memory operation window, the memory device having a left charge storage site for storing
at least a first bit and a right charge storage site for storing at least a second bit in which sufficient charge is trapped
in the left charge storage site to establish a negative threshold voltage, comprising:
a channel region disposed between a drain region and a source region;
a charge trapping structure overlying the channel region; and
a conductive layer overlying the charge trapping structure;
a bias condition applied to the memory device that causes electron injection to the right charge storage site while the left
charge storage site traps sufficient charge to establish the negative threshold voltage.
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