| US 7,512,012 B2 | ||
| Non-volatile memory and manufacturing method and operating method thereof and circuit system including the non-volatile memory | ||
| Ming-Chang Kuo, Hsinchu (Taiwan) | ||
| Assigned to Macronix International Co., Ltd., Hsinchu (Taiwan) | ||
| Filed on Apr. 30, 2007, as Appl. No. 11/742,345. | ||
| Prior Publication US 2008/0266960 A1, Oct. 30, 2008 | ||
| Int. Cl. G11C 16/04 (2006.01) | ||
| U.S. Cl. 365—185.26 [365/185.12; 365/185.1; 365/185.01; 365/185.18; 257/314; 257/315; 257/318; 257/E21.409; 257/E29.226; 438/257] | 53 Claims |
| 1. A non-volatile memory, comprising:
a memory cell, disposed on a substrate, the memory cell comprising:
a first unit, comprising:
a first gate; and
a first charge trapping layer and a second charge trapping layer, respectively disposed at both sides of the first gate;
a semiconductor layer, disposed on the substrate and covering the first unit, the lateral dimension of the semiconductor layer
being greater than the lateral dimension of the first unit;
a second unit, disposed on the semiconductor layer, the second unit being in mirror symmetry to the first unit with the semiconductor
layer as a symmetry axis, the second unit comprising:
a second gate, disposed on the semiconductor layer; and
a third charge trapping layer and a fourth charge trapping layer, respectively disposed at both sides of the second gate;
and
a doped region, disposed in both sides of the semiconductor layer and serving as a common source/drain region of both the
first unit and the second unit.
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