| US 7,512,004 B2 | ||
| Semiconductor memory device having stacked gate including charge accumulation layer and control gate and test method thereof | ||
| Tokumasa Hara, Kawasaki (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Jun. 20, 2007, as Appl. No. 11/765,749. | ||
| Claims priority of application No. 2006-171856 (JP), filed on Jun. 21, 2006. | ||
| Prior Publication US 2007/0297262 A1, Dec. 27, 2007 | ||
| Int. Cl. G11C 16/04 (2006.01); G11C 11/34 (2006.01) | ||
| U.S. Cl. 365—185.14 [365/185.05; 365/185.26; 365/201] | 11 Claims |
| 1. A semiconductor memory device comprising:
a memory cell which has a first MOS transistor including a charge accumulation layer and a control gate formed on the charge
accumulation layer;
a word line which is connected to the control gate of the first MOS transistor and is set in a non-selected state at a test
operation time of the memory cell;
a bit line which is connected to a drain of the first MOS transistor and is applied with first voltage at the test operation
time and at a data program operation time with respect to the memory cell;
a source line which is connected to a source of the first MOS transistor and is set at potential lower than that of the bit
line at the test operation time;
a column gate including a second MOS transistor having current path connected to the bit line to transfer the first voltage
to the bit line at the test operation time; and
a power supply decode circuit which applies a second voltage to a gate of the second MOS transistor at the program operation
time and applies a third voltage lower than the second voltage at the test operation time.
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