| US 7,512,000 B2 | ||
| Memory unit | ||
| Ming-Chang Kuo, Hsinchu (Taiwan) | ||
| Assigned to MACRONIX International Co., Ltd., Hsinchu (Taiwan) | ||
| Filed on Apr. 16, 2007, as Appl. No. 11/735,910. | ||
| Prior Publication US 2008/0253189 A1, Oct. 16, 2008 | ||
| Int. Cl. G11C 16/04 (2006.01) | ||
| U.S. Cl. 365—185.08 [365/185.05; 365/185.01] | 10 Claims |
| 1. A memory unit, comprising:
a first load unit, having a first end coupled to a first voltage, and a second end coupled to a first contact;
a second load unit, having a first end coupled to the first voltage, and a second end coupled to a second contact;
a first metal-oxide-semiconductor (MOS) transistor, having a first end coupled to the first contact, a second end coupled
to a second voltage, and a gate coupled to the second contact;
a second MOS transistor, having a first end coupled to the second contact, a second end coupled to a third voltage, and a
gate coupled to the first contact;
a first non-volatile device having a split-gate structure, and having a control gate coupled to a first control bias voltage,
a select gate coupled to a first select bias voltage, a first end coupled to the first contact, and a second end coupled to
a first bit line; and
a second non-volatile device having a split-gate structure, and having a control gate coupled to a second control bias voltage,
a select gate coupled to a second select bias voltage, a first end coupled to the second contact, and a second end coupled
to a second bit line.
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