| US 7,511,997 B2 | ||
| Semiconductor memory device | ||
| Haruki Toda, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Feb. 24, 2006, as Appl. No. 11/360,536. | ||
| Claims priority of application No. 2005-079443 (JP), filed on Mar. 18, 2005. | ||
| Prior Publication US 2006/0209593 A1, Sep. 21, 2006 | ||
| Int. Cl. G11C 11/34 (2006.01) | ||
| U.S. Cl. 365—185.03 | 14 Claims |

| 1. A semiconductor memory device comprising:
a memory cell array with memory cells arranged therein, each memory cell being settable to have one of plural physical quantity
levels, simultaneously selected two memory cells constituting a pair cell serving as a data storage unit; and
a read/write circuit for reading data from the memory cell array and writing data into the memory cell array, wherein
each memory cell is set to have one in N (where N is an integer equal to three or more) physical quantity levels, a highest
or a lowest level of the N physical quantity levels is defined as a base level, and a first of the cells of the pair cell
is set to the base level and a second of the cells of the pair cell is set to a different level than the base level in two
memory cells therein, thereby storing M-value data defined by M=2n (where M=2(N−1) and “n” is an integer equal to two or more), the M-value data being defined by such M combination states that
differences of the base level of the first of the cells and plural other levels of the second of the cells are different from
each other.
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