| US 7,511,993 B2 | ||
| Phase change memory device and related programming method | ||
| Byung-Gil Choi, Yongin-si (Korea, Republic of); Du-Eung Kim, Yongin-si (Korea, Republic of); Beak-Hyung Cho, Hwaseong-si (Korea, Republic of); and Woo-Yeong Cho, Suwon-si (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do (Korea, Republic of) | ||
| Filed on Mar. 15, 2007, as Appl. No. 11/724,268. | ||
| Claims priority of application No. 10-2006-0029692 (KR), filed on Mar. 31, 2006. | ||
| Prior Publication US 2007/0230240 A1, Oct. 04, 2007 | ||
| Int. Cl. G11C 11/00 (2006.01) | ||
| U.S. Cl. 365—163 [365/148; 365/230.06] | 17 Claims |
| 1. A phase change memory device, comprising:
a memory cell array comprising a plurality of memory cells; and
a write driver circuit adapted to provide a set current and a reset current to a selected memory cell among the plurality
of memory cells;
wherein the write driver circuit comprises a set current driver providing a set current and controlled by a set current controller
operating in response to a set control signal and a set direct current (DC) voltage, and a reset current driver providing
a reset current and controlled by a reset current controller operating in response to a reset control signal and a reset DC
voltage.
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