a gate line and a gate pad on a substrate;

a gate insulating layer on an entire surface of the substrate including the gate line except the gate pad;

a data line and a data pad on the gate insulating layer;

a thin film transistor at a crossing portion of the gate line and the data line;

a passivation layer on the entire surface of the substrate including the thin film transistor except the gate pad and data pad;

an overcoat layer on the passivation layer;

a pixel electrode in contact with the thin film transistor through a contact hole formed in the passivation layer and the overcoat layer;

a first transparent conductive layer directly on an open region of the gate pad to an edge thereof, wherein the first transparent conductive layer is formed at a region where all the gate insulating layer, the a passivation layer and the overcoat layer is removed on said open region including to said edge; and

a second transparent conductive layer directly on an open region of the data pad to an edge thereof, wherein the second transparent conductive layer is formed at a region where all the a passivation layer and the overcoat layer is removed on said open region including to said edge, wherein a semiconductor layer is below the data pad.