a first means for generating a thermal voltage and multiplying the thermal voltage to obtain a first multiplied voltage, the multiplied voltage not being equal to the thermal voltage, wherein the thermal voltage is approximately proportional to absolute temperature, wherein the first means includes:

a first field effect transistor (FET) having a source, a gate and a drain, the source of the first FET being connected to a power supply for the reference voltage circuit and the gate of the first FET being connected to the drain of the first FET,

a second FET having a source, a gate and a drain, the source of the second FET being connected to the power supply, and the gate of the second FET being connected to the gate of the first FET,

a third FET having a source, a gate and a drain, the source of the third FET being connected to the power supply, and the gate of the third FET being connected to the gate of the first FET,

a fourth FET having a source, a gate and a drain, the drain of the fourth FET being connected to the drain of the first FET and the gate of the fourth FET being connected to the drain of the fourth FET,

a fifth FET having a source, a gate and a drain, the drain of the fifth FET being connected to the drain of the second FET and the gate of the fifth FET being connected to the drain of the second FET,

a first bipolar transistor having an emitter, a collector and a base, the base and the collector of the first bipolar transistor being connected to a ground for the reference voltage circuit,

a second bipolar transistor having an emitter, a collector and a base, the base and the collector of the second bipolar transistor being connected to the ground, and the emitter for the second bipolar transistor being connected to the source of the fifth FET, and

a first resistor connected between the source of the fourth FET and the emitter or the first bipolar transistor;

a second means for generating an inverse thermal voltage that is approximately inversely proportional to absolute temperature and multiplying the inverse thermal voltage to obtain a second multiplied voltage, wherein the second means includes:

a sixth FET having a source, a gate and a drain, the source of the sixth FET being connected to the power supply,

a seventh FET having a source, a gate and a drain, the source of the seventh FET being connected to the power supply, and the gate of the seventh FET being connected to the gate of the sixth FET,

an eighth FET having a source, a gate and a drain, the source of the eighth FET being connected to the power supply, and the gate of the eighth FET being connected to the gate of the sixth FET,

a ninth FET having a source, a gate and a drain, the drain of the ninth FET being connected to the drain of the sixth FET, and the gate of the ninth FET being connected to the drain of the ninth FET,

a tenth FET having a source, a gate and a drain, the drain of the tenth FET being connected to the drain of the seventh FET, and the gate of the tenth FET being connected to the drain of the ninth FET,

a third bipolar transistor having an emitter, a collector and a base, the base and the collector of the third bipolar transistor being connected to the ground, and the emitter for the third bipolar transistor being connected to the source of the ninth FET, and

a second resistor connected between the source of the tenth FET and the ground; and,

a third means for summing the first multiplied voltage with the second multiplied voltage to obtain a reference voltage, wherein the third means includes:

a third resistor connected between the drain of the eighth FET and the ground, and

a fourth resistor connected between the drain of the third FET and the drain of the eighth FET.