| US 7,511,358 B2 | ||
| Nonvolatile memory device having multi-bit storage and method of manufacturing the same | ||
| Byung-yong Choi, Suwon-si (Korea, Republic of); Choong-ho Lee, Seongnam-si (Korea, Republic of); and Dong-gun Park, Seongnam-si (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., (Korea, Republic of) | ||
| Filed on Sep. 07, 2006, as Appl. No. 11/517,595. | ||
| Claims priority of application No. 10-2005-0083582 (KR), filed on Sep. 08, 2005. | ||
| Prior Publication US 2007/0054448 A1, Mar. 08, 2007 | ||
| Int. Cl. H01L 29/06 (2006.01) | ||
| U.S. Cl. 257—618 [257/324; 257/353; 257/E29.17] | 10 Claims |
| 1. A nonvolatile memory device comprising:
a fin type active region formed on a semiconductor substrate, a portion of the fin type active region protruding from the
semiconductor substrate, the protruding portion of the fin type active region comprising a first side surface, a second side
surface, and a top surface;
a gate formed along the first side surface, the top surface, and the second side surface of the fin type active region;
a pair of local charge storage layer patterns formed under the gate, and physically isolated from each other by an extending
portion of the gate that extends from at least one of the first side surface and the second side surface of the fin type active
region, wherein the pair of local charge storage layer patterns extends along the first side surface, the top surface, and
the second side surface of the protruding fin type active region;
a charge blocking layer interposed between the local charge storage patterns and the gate;
a tunneling dielectric layer interposed between the local charge storage layer patterns and the active region for charge tunneling;
and
a gate dielectric layer extending between a side surface of the local charge storage layer pattern and the gate by being between
the portion of the fin type active region protruding from the semiconductor substrate and the extending portion of the gate.
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