| US 7,511,349 B2 | ||
| Contact or via hole structure with enlarged bottom critical dimension | ||
| Ming-Huan Tsai, Hsinchu (Taiwan); Fang-Cheng Chen, Hsin-Chu (Taiwan); Chao-Cheng Chen, Shin-Chu County (Taiwan); and Syun-Ming Jang, Hsin-Chu (Taiwan) | ||
| Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (Taiwan) | ||
| Filed on Aug. 19, 2005, as Appl. No. 11/207,450. | ||
| Prior Publication US 2007/0040188 A1, Feb. 22, 2007 | ||
| Int. Cl. H01L 29/76 (2006.01); H01L 29/94 (2006.01); H01L 31/00 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01) | ||
| U.S. Cl. 257—382 [257/751; 257/774; 257/775; 257/E29.112] | 16 Claims |
| 1. An integrated circuit chip comprising:
a buffer layer over an underlying layer, the buffer layer being formed of a dielectric material;
a dielectric layer over the buffer layer;
a hole formed in and extending through the dielectric layer and the buffer layer,
wherein the hole opens to the underlying layer, and
wherein the hole comprises a buffer layer portion at the buffer layer and a dielectric layer portion at the dielectric layer,
wherein at least part of the buffer layer portion of the hole has a larger cross-section area than a smallest cross-section
area of the dielectric layer portion of the hole; and
a conductive and substantially conformal barrier layer covering substantially all surfaces of the dielectric layer and the
buffer layer in the hole.
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