| US 7,511,348 B2 | ||
| MOS transistors with selectively strained channels | ||
| Chih-Hsin Ko, Fongshan (Taiwan); Wen-Chin Lee, Hsin-Chu (Taiwan); Chung-Hu Ke, Taipei (Taiwan); and Hung-Wei Chen, Hsinchu (Taiwan) | ||
| Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (Taiwan) | ||
| Filed on Mar. 13, 2007, as Appl. No. 11/717,450. | ||
| Prior Publication US 2008/0224225 A1, Sep. 18, 2008 | ||
| Int. Cl. H01L 29/76 (2006.01) | ||
| U.S. Cl. 257—371 [257/382; 257/392; 257/18; 257/E27.062; 257/E27.064] | 9 Claims |
| 1. A semiconductor integrated circuit apparatus, comprising:
a semiconductor substrate;
a first transistor, including a first well formed in said semiconductor substrate, and a first gate structure disposed on
said semiconductor substrate and extending away from said semiconductor substrate, said first gate structure including a first
gate electrode overlying said first well, and said first gate structure further including a stressor that produces a first
stress in said first well, said first gate electrode disposed between said stressor and said semiconductor substrate;
a second transistor, including a second well formed in said semiconductor substrate, and a second gate structure disposed
on said semiconductor substrate and extending away from said semiconductor substrate, said second gate structure including
a second gate electrode having a uniform composition overlying said second well, and said second gate electrode extending
further from said semiconductor substrate than said first gate electrode; and
a layer of material disposed in contact with said first gate structure and said second gate structure, said layer of material
producing a second stress in said second well, the second stress having an opposite type of stress than the first stress.
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