| US 7,511,347 B2 | ||
| Semiconductor integrated circuit for high-speed, high-frequency signal transmission | ||
| Kazuhiko Kajigaya, Tokyo (Japan); and Kanji Otsuka, Tokyo (Japan) | ||
| Assigned to Elpida Memory Inc., Tokyo (Japan) | ||
| Filed on Nov. 18, 2005, as Appl. No. 11/281,743. | ||
| Claims priority of application No. 2004-338237 (JP), filed on Nov. 22, 2004. | ||
| Prior Publication US 2006/0108640 A1, May 25, 2006 | ||
| Int. Cl. H01L 27/092 (2006.01) | ||
| U.S. Cl. 257—371 [257/E27.062] | 11 Claims |

| 8. A semiconductor integrated circuit comprising:
a pair of MOS transistors which are formed in a same well on a semiconductor substrate and arranged adjacent to each other
at a distance such that charge exchange between capacitances of respective drain diffusion layers is possible; and
a wiring structure which is formed to apply differential signals to respective gates of said pair of MOS transistors and to
apply a common potential to respective sources of said pair of MOS transistors; and
a differential circuit comprised of said pair of MOS transistors,
wherein in said wiring structure, differential input signals include a positive signal and an inverted signal, said positive
signal is applied to one gate of said pair of MOS transistors, said inverted signal is applied to the other gate of said pair
of MOS transistors, and differential output signals are output from said drain diffusion layer of each of said pair of MOS
transistors;
and in addition to said pair of MOS transistors, one or more other MOS transistors are formed in the same well and are arranged
with a distance such that interference due to said charge exchange between said drain diffusion layers of said pair of MOS
transistors and drain diffusion layers of said other MOS transistors does not occur.
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