| US 7,511,342 B2 | ||
| Semiconductor device having SOI structure and method for manufacturing the same | ||
| Mikio Tsujiuchi, Tokyo (Japan); Toshiaki Iwamatsu, Tokyo (Japan); and Shigeto Maegawa, Tokyo (Japan) | ||
| Assigned to Renesas Technology Corp., Tokyo (Japan) | ||
| Filed on Jan. 30, 2006, as Appl. No. 11/341,444. | ||
| Claims priority of application No. 2005-035985 (JP), filed on Feb. 14, 2005; and application No. 2005-372223 (JP), filed on Dec. 26, 2005. | ||
| Prior Publication US 2006/0180861 A1, Aug. 17, 2006 | ||
| Int. Cl. H01L 31/0392 (2006.01) | ||
| U.S. Cl. 257—347 [257/E27.112; 438/149] | 10 Claims |
| 1. A semiconductor device comprising:
a substrate including an underlying silicon substrate, a buried insulator, and a semiconductor layer;
a first gate electrode formed on a gate insulator on the semiconductor layer;
a first impurity diffused region formed in a region around the first gate electrode in the direction of the length of the
first gate electrode in the semiconductor layer by implanting with an impurity of a first conductivity type;
a second impurity diffused region formed in a region in the semiconductor layer in the direction of an extension line of the
length of the first gate electrode by implanting with an impurity of a second conductivity type opposite the first conductivity
type;
a first insulator which is formed at least on a region of the semiconductor layer between the second impurity diffused region
and the first gate electrode; and
a second gate electrode formed on the first insulator between the second impurity diffused region and the first gate electrode,
wherein the first insulator has a complete isolation region on both sides of the width of the first gate electrode at an end
of the first gate electrode opposed to the second gate electrode, the complete isolation region penetrating through the semiconductor
layer down to the buried insulator.
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