| US 7,511,338 B2 | ||
| Semiconductor device and manufacturing method of the same | ||
| Toshihide Nabatame, Tokyo (Japan); Masaru Kadoshima, Tokyo (Japan); and Hiroyuki Takaba, Tokyo (Japan) | ||
| Assigned to Renesas Technology Corp., Tokyo (Japan); and Tokyo Electron Limited, Tokyo (Japan) | ||
| Filed on Sep. 06, 2006, as Appl. No. 11/515,797. | ||
| Claims priority of application No. 2005-257510 (JP), filed on Sep. 06, 2005. | ||
| Prior Publication US 2007/0096157 A1, May 03, 2007 | ||
| Int. Cl. H01L 23/62 (2006.01) | ||
| U.S. Cl. 257—338 [257/357; 257/369] | 6 Claims |
| 1. A semiconductor device comprising:
an n channel MIS transistor with a first gate electrode formed in a first region on a main surface of a semiconductor substrate;
and
a p channel MIS transistor with a second gate electrode having a work function higher than a work function of said first gate
electrode formed in a second region on said main surface,
wherein said first and second gate electrodes are formed of the same metal,
wherein oxygen concentration in said second gate electrode is higher than oxygen concentration in said first gate electrode,
and
wherein a hydrogen barrier film is formed over said second gate electrode and is not formed over said first gate electrode.
|