a memory cell, which comprises:

a substrate with a first insulating layer disposed thereon;

a source region, channel region and drain region stacked on the substrate sequentially as a transistor body;

a tunnel dielectric layer on a sidewall of the transistor body;

a floating gate disposed on the tunnel dielectric layer;

a second insulating layer covering the floating gate;

a control gate disposed on the second insulating layer, isolated from the floating gate by the second insulating layer and from the transistor body by the tunnel dielectric layer;

a bit line electrically connected to the top of the transistor body via a bit line contact plug;

a word line electrically connected to the control gate via a word line contact plug, wherein the bit line and word line are isolated by a third insulating layer; and

a source line disposed in the first insulating layer of the substrate, in contact with the source region,

wherein the top of the floating gate is between the upper and bottom surface of the channel regions and the top of the control gate is not over the upper surface of the channel region.