US 7,510,965 B2
Method for fabricating a dual damascene structure
Hong Ma, Singapore (Singapore)
Assigned to United Microelectronics Corp., Science-Based Industrial Park, Hsin-Chu (Taiwan)
Filed on Nov. 30, 2006, as Appl. No. 11/564,847.
Prior Publication US 2008/0132067 A1, Jun. 05, 2008
Int. Cl. H01L 21/4763 (2006.01)
U.S. Cl. 438—638  [438/639; 438/667; 438/672] 30 Claims
OG exemplary drawing
 
1. A method for fabricating a dual damascene structure, comprising:
providing a substrate having a conductive layer, a first etching stop layer, a dielectric layer, and a first photoresist layer positioned on the surface of the substrate in order;
patterning the first photoresist layer so as to defined a via pattern on the first photoresist layer;
performing a first etching process to remove a portion of the dielectric layer through the via pattern, until the etching stop layer is exposed so as to form a via hole structure in the dielectric layer;
performing a first ash process to remove the first photoresist layer by providing a gas comprising carbon monoxide (CO-containing gas);
filling gap-fill polymer (GFP) materials into the via hole structure;
forming a second photoresist layer on the substrate;
patterning the second photoresist layer to define a trench pattern;
performing a second etching process to etch the dielectric layer though the trench pattern so as to form a trench structure on the upper portion of the dielectric layer, the trench structure exposing the via hole structure;
removing the second photoresist layer and the GFP materials in the via hole structure; and
removing the first etching stop layer exposed by the via hole structure.