| US 7,510,940 B2 | ||
| Method for fabricating dual-gate semiconductor device | ||
| Chen-Nan Yeh, Hsin Chih (Taiwan); Mong Song Liang, Hsin-Chu (Taiwan); Ryan Chia-Jen Chen, Chiaya (Taiwan); and Yuan-Hung Chiu, Taipei (Taiwan) | ||
| Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (Taiwan) | ||
| Filed on Feb. 16, 2007, as Appl. No. 11/707,490. | ||
| Prior Publication US 2008/0197420 A1, Aug. 21, 2008 | ||
| Int. Cl. H01L 21/336 (2006.01) | ||
| U.S. Cl. 438—283 [257/E21.623] | 14 Claims |
| 1. A method of fabricating a dual-gate semiconductor device, comprising:
forming an asymmetric gate stack having a first portion and a second portion, the first portion comprising a metal layer;
etching a second gate structure in the second portion and partially etching a first gate structure in the first portion, wherein
the partial etch of the first gate structure does not remove the metal layer;
forming a dielectric layer on at least a portion of each gate structure;
etching recesses for a source region and a drain region adjacent the second gate structure and simultaneously removing the
metal layer except that portion forming part of the first gate structure; and
forming a source region in the source-region recess and a drain region in the drain region recess.
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