| US 7,510,937 B2 | ||
| Nonvolatile semiconductor memory device and fabrication method for the same | ||
| Keita Takahashi, Nara (Japan) | ||
| Assigned to Panasonic Corporation, Osaka (Japan) | ||
| Filed on Jan. 28, 2008, as Appl. No. 12/20,744. | ||
| Claims priority of application No. 2007-149074 (JP), filed on Jun. 05, 2007. | ||
| Prior Publication US 2008/0303078 A1, Dec. 11, 2008 | ||
| Int. Cl. H01L 21/336 (2006.01) | ||
| U.S. Cl. 438—270 [257/318; 257/316; 257/326; 257/E21.179; 257/E21.18; 257/E21.21; 257/E21.423; 257/E21.679] | 13 Claims |
| 1. A fabrication method for a nonvolatile semiconductor memory device comprising a memory cell area including memory cells
and a peripheral circuit area adjacent to the memory cell area and including peripheral transistors, the method comprising
the steps of:
(1) forming a first active region in the memory cell area and a second active region in the peripheral circuit area in a substrate
by forming isolation insulating films in the memory cell area and the peripheral circuit area so as to be away from a boundary
between the memory cell area and the peripheral circuit area;
(2) forming a bottom insulating film and an intermediate charge trap film sequentially over the entire surface of the substrate;
(3) removing a portion of the intermediate charge trap film formed in the peripheral circuit area using a first mask film;
(4) forming a gate insulating film in the peripheral circuit area and also at least part of a top insulating film in the memory
cell area;
(5) forming a gate electrode film on the top insulating film and the gate insulating film; and
(6) forming gate electrodes of memory cells and gate electrodes of peripheral transistors by patterning the gate electrode
film,
wherein the step (3) comprises a step of aligning an end of the first mask film with the boundary in the substrate.
|